Micro-Controller Evaluations
- A Unified Cryptoprocessor for Lattice-based Signature and Key-exchange: Proposing a compact, unified and instruction-set cryptoprocessor architecture for performing both lattice-based digital signature and key exchange operations. [M21]
- AVRNTRU: Lightweight NTRU-based Post-Quantum Cryptography for 8-bit AVR Microcontrollers: Presentation of Avrntru, a highly-optimized implementation of NTRUEncrypt for 8-bit AVR microcontrollers. [CGR21]
- An Area-Efficient SPHINCS+ Post-Quantum Signature Coprocessor: Providing an area-efficient FPGA implementation of SPHINCS+. [BUG21]
- Compact Coprocessor for KEM Saber: Novel Scalable Matrix Originated Processing: Present a novel compact coprocessor for KEM Saber on the field-programmable gate array (FPGA) platform. [HLX21]
- Efficient Microcontroller Implementation of BIKE: Investigation of various techniques to achieve an efficient and secure implementation of BIKE on embedded devices. [BOG20]
- Efficient hardware/software co-design for post-quantum crypto algorithm SIKE on ARM and RISC-V based microcontrollers: Hardware/software co-design methodologies for SIKE and Integration of a redundant number based finite field accelerator into two microcontroller platforms based on ARM and RISC-V. [RFS20]
- Implementing RLWE-based Schemes Using an RSA Co-Processor: [AHH18]
- Implementing and Benchmarking Three Lattice-Based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign: Presenting the results of implementing and benchmarking three lattice-based key encapsulation mechanisms (KEMs) of the 2nd round of the NIST standardization process. [DFA19]
- Lightweight Post-quantum Key Encapsulation for 8-bit AVR Microcontrollers: New techniques for the optimization of the ring arithmetic of ThreeBears to achieve either high speed or low RAM footprint. [CGR21]
- Optimized Software Implementations of CRYSTALS-Kyber, NTRU, and Saber Using NEON-Based Special Instructions of ARMv8: Optimizations of two NIST 3rd round candidates: SIKE and Dilithium. [DK21]
- Post-Quantum Cryptography with Contemporary Co-Processors: Proposing the Kronecker+ algorithm for polynomial multiplication in rings of the form Z /(X n + 1). [BRV20]
- Post-Quantum Key Exchange on ARMv8-A: A New Hope for NEON Made Simple: Time-constant and vector-optimized implementations of NewHope and NewHope-Simple for ARMv8-A 64-bit processors which target high-speed applications. [SD18]
- RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography: RISQ-V, an enhanced RISC-V architecture that integrates a set of powerful tightly coupled accelerators to speed up lattice-based PQC. [FSS20]
- Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols: Efficient crypto-processor achieving up to an order of magnitude improvement in performance and energy-efficiency compared to state-of-the-art hardware implementations. [BUC19]
- Speeding-up Ideal Lattice-Based Key Exchange Using a RSA/ECC Coprocessor: [GMR20]
- Towards Practical Microcontroller Implementation of the Signature Scheme Falcon: In this work, we analyze the practicability of the signature scheme Falcon with respect to its suitability for embedded microcontroller platforms. [OSH19]
- Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V: Presenting an improved RISC-V co-processor for post-quantum security. [FSM19]
- VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture: Presenting a domain-specific vector processor, VPQC, leveraging the extensible RISC-V architecture. [XHY20]
Last modified February 12, 2022